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  5. A scalable multiprocessor architecture using Cartesian Network-Relative Addressing

A scalable multiprocessor architecture using Cartesian Network-Relative Addressing

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Author(s)
Morrison, Joseph Derek
Advisor(s)
Stephen A. Ward.
Date Issued
1989
Publisher
Massachusetts Institute of Technology
Description
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989.
Includes bibliographical references (leaves 101-102).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Persistent DSpace Link
http://hdl.handle.net/1721.1/14200
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