The design and implementation of a 3D graphics pipeline for the raw reconfigurable architecture
Name
57396246-MIT.pdf
Description
Full printable version
Size
14.39 MB
Format
Adobe PDF
Checksum (MD5)
4e0aae11a85615a9338ccdc2b28bf60d
Author(s)
Taylor, Kenneth William, 1980-
Advisor(s)
Anant Agarwal.
Date Issued
2004
Publisher
Massachusetts Institute of Technology
Abstract
This thesis presents the design and implementation of a 3D graphics pipeline, built on top of the "Raw" processor developed at MIT. The Raw processor consists of a tiled array of CPUs, caches, and routing processors connected by several high-speed networks, and can be treated as a coarse-grained reconfigurable architecture. The graphics pipeline has four stages, and four-way parallelism in each stage, and is mapped on to a 16-tile Raw array. It supports basic rendering functions such as hardware transform and lighting, perspective correct texture mapping, and depth buffering, and is intended to be used as a slave processor receiving rendering commands from a host system. The design process is described in detail, along with difficulties encountered along the way, and a comprehensive performance evaluation is carried out. The paper concludes with many suggestions for architectural and performance improvements to be made over the initial design.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (p. 345-346).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Persistent DSpace Link
