First Demonstration of a Self-Aligned GaN p-FET
Name
PID6055875-1.pdf
Description
Accepted version
Size
1.45 MB
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Unknown
Checksum (MD5)
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Author(s)
Chowdhury, Nadim
Xie, Qingyun
Yuan, Mengyang
Rajput, Nitul S.
Xiang, Peng
Cheng, Kai
Then, Han Wui
Palacios, Tomas
Date Issued
2019
Journal
Technical Digest - International Electron Devices Meeting, IEDM
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Chowdhury, Nadim, Xie, Qingyun, Yuan, Mengyang, Rajput, Nitul S, Xiang, Peng et al. 2019. "First Demonstration of a Self-Aligned GaN p-FET." Technical Digest - International Electron Devices Meeting, IEDM, 2019-December.
Version
Author's final manuscript
Abstract
In this work, we demonstrate a self-aligned p-FET with a GaN/Al0 2Ga0 8N (20 nm)/GaN heterostructure grown by metal-organic-chemical vapor deposition (MOCVD) on Si substrate. Our 100 nm channel length device with recess depth of 70 nm exhibits a record ON-resistance of 400 Ωmm and ON-current over 5 mA/mm with ON-OFF ratio of 6×105 when compared with other p-FET demonstrations based on GaN/AlGaN heterostructure. The device shows E-mode operation with a threshold voltage of -1 V, making it a promising candidate for GaN-based complementary circuit that can be integrated on a Silicon platform. A monolithically integrated n-channel transistor with p-GaN gate is also demonstrated. The potential of the reported p-FET for complementary logic application is evaluated through industry-standard compact modeling and inverter circuit simulation.
MIT Department
Massachusetts Institute of Technology. Microsystems Technology Laboratories
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DOI of Published Version
https://doi.org/10.1109/IEDM19573.2019.8993569
