Improved handling of the decoding operation in the Presto compiler
Name
62242432-MIT.pdf
Description
Full printable version
Size
2.82 MB
Format
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Checksum (MD5)
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Author(s)
Dong, Wenyan, 1980-
Advisor(s)
Karen Pieper and Arvind.
Date Issued
2004
Publisher
Massachusetts Institute of Technology
Abstract
This thesis presents a research project on decoder related optimizations in HDL de- signs. The goal of the research is to improve design synthesis quality-of-result, mainly in terms of area; this involves sharing decoders driven by related inputs, and map decoders using fewer number of boolean gates. Algorithms presented in this thesis were implemented in the Presto HDL compiler. A series of tests were conducted using real-world HDL designs in order to determine how effective these optimizations are.
Description
Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (leaves 62-63).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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