Circuit implementations for high-efficiency video coding tools
Name
820028934-MIT.pdf
Description
Full printable version
Size
508.8 KB
Format
Adobe PDF
Checksum (MD5)
e278f4764df1e27c61a763d0219a06d0
Author(s)
Tikekar, Mehul (Mehul Deepak)
Advisor(s)
Anantha P. Chandrakasan.
Date Issued
2012
Publisher
Massachusetts Institute of Technology
Abstract
High-Efficiency Video Coding (HEVC) is planned to be the successor video standard to the popular Advanced Video Coding (H.264/AVC) with a targeted 2x improvement in compression at the same quality. This improvement comes at the cost of increased complexity through the addition of new coding tools and increased computation in existing tools. The ever-increasing demand for higher resolution video further adds to the computation cost. In this work, digital circuits for two HEVC tools - inverse transform and deblocking filter are implemented to support Quad-Full HD (4K x 2K) video decoding at 30fps. Techniques to reduce power and area cost are investigated and synthesis results in 40nm CMOS technology and Virtex-6 FPGA platform are presented.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 71-72).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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