The design of a high precision, wide common mode range auto-zero comparator

Abstract

This thesis discusses the design and analysis of a high common-mode input auto-zero comparator for use in a Hot Swap controller. Comparators are essential building blocks within the current limit detection schemes of Hot Swap controllers. However, the current limit detection scheme places a sense resistor in the current path, burning static power. Reducing this power consumption while maintaining the overall accuracy of the detector can be done by decreasing the full scale sense voltage across the sense resistor, decreasing the size of the sense resistor, and increasing the overall accuracy of the comparator. This is realized by using an auto-zero comparator designed in Linear Technology's 0.6 [mu]m BiCMOS process. The overall topology uses the closed loop offset storage with an auxiliary amplifier scheme. The input and auxiliary amplifier are based on the fully differential folded cascode topology with some key changes. The comparator is a typical PMOS comparator with internal hysteresis and additional circuitry added to maintain symmetry for as long as possible. A Widlar bandgap-based circuit provides the necessary internal reference. The comparator was designed and verified using LTspice and Linear Technologys in house models. The resulting design has an absolute accuracy better than +/-200 [mu]V over temperature, increasing the relative accuracy with the sense resistor value halved from previous designs. Additionally, the comparator can handle inputs from zero to sixty volts and settles to a new offset sample in less than 3 [mu]s.