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Full utilization, fairness, and access delay on high speed slotted bus networks

dc.contributor.advisorRobert G. Gallager.en_US
dc.contributor.authorChiu, Angela Lanen_US
dc.date.accessioned2005-08-18T19:11:24Z
dc.date.available2005-08-18T19:11:24Z
dc.date.copyright1997en_US
dc.date.issued1997en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/10264
dc.descriptionThesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.en_US
dc.descriptionIncludes bibliographical references (p. 89-92).en_US
dc.description.statementofresponsibilityby Angela Lan Chiu.en_US
dc.format.extent92 p.en_US
dc.format.extent5167673 bytes
dc.format.extent5167429 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Scienceen_US
dc.titleFull utilization, fairness, and access delay on high speed slotted bus networksen_US
dc.typeThesisen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc37016747en_US


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