Analog-digital co-existence in 3D-IC

Abstract

Ubiquitous mobile communication creates an increasing demand for high data rates, complex modulation schemes and low power design. The cost and performance benefits of conventional lithographic scaling are diminishing as process cost increases exponentially. 3D integration has the potential to keep driving performance forward while keeping cost down. The possibility to integrate separate dies with low-parasitic, dense interconnect and shorter routing provides area and power benefits. However, new challenges must be addressed in order to enable design in this new dimension and provide system level improvements. This thesis explores the impact, challenges and advantages of using 3D integration for combining digital and analog circuits for RF applications. The use of a vertical solenoid inductor in a Voltage Controlled Oscillator (VCO) is proposed. The inductor design utilizes the through-silicon-vias of the 3D stack as part of its geometry. The solenoid inductor exhibits a 28%larger inductance and a 6 dB higher quality factor compared to a conventional planar inductor occupying the same area. The VCO circuit phase noise is improved by 6 dB and exhibits an improved immunity to coupling from adjacent digital clock lines routed on the bottom tier of the 3D stack. An efficient hardware implementation is presented for an LTE uplink channel. The proposed design processes input data for cellular transmission. The core of the computation includes a variable-length, high-order, mixed-radix FFT and IFFT blocks. The use of energy efficient circuits and algorithms enables achieving an energy efficiency of up to 95 pJ/Sample and additional power savings of up to 24% for different operation modes. Both designs are combined along with digital-to-analog conversion to create a partial cellular transmitter in 3D-IC. Highly flexible and configurable design allows for various partitioning of the system. The 3D design has a digital link energy efficiency of up to 0.37 pJ/bit, compared to the 33.3 pJ/bit consumed in a multiple die partitioning and 0.83 pJ/bit for a 2.5D interposer emulated design. The use of the solenoid VCO along with digital-analog partitioning between the die tiers enables high immunity to noise and reduction of spurs at the VCO output.