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dc.contributor.advisorAkintunde I. (Tayo) Akinwande.en_US
dc.contributor.authorGuerrera, Stephen A. (Stephen Angelo)en_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2016-07-18T20:04:21Z
dc.date.available2016-07-18T20:04:21Z
dc.date.copyright2016en_US
dc.date.issued2016en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/103725
dc.descriptionThesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.en_US
dc.descriptionCataloged from PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 231-241).en_US
dc.description.abstractField emitter arrays (FEAs) are a promising class of cold electron sources with applications in RF amplifiers, terahertz sources, lithography, imaging, and displays. FEAs are yet to achieve widely implemented because of serious challenges which have limited their viability in systems that require advanced electron sources. We identified four major challenges that posed significant barriers to the application of field emitter arrays in systems. These challenges are (1) charge injection and breakdown of the insulator between the emitter and the extraction gate, (2) thermal runaway due to Joule heating or micro-plasma discharge, (3) back-ion bombardment resulting in emitter tip damage (4) large capacitance between the gate and the substate that limits switching performance. In this thesis, we address these challenges with a new device architecture that consists of a sharp silicon emitter atop a silicon nanowire embedded in a dielectric matrix of SiO₂ and SiNx. The 10-[mu]m tall, 200-nm diameter silicon nanowire limits current and improves reliability through velocity saturation and the pinch-off of majority carriers. The 2-[mu]m thick SiO₂ insulator between the gate and the substrate and the conformal dielectric matrix that embeds the nanowire current limiters prevents charge injection and minimizes the capacitance between the gate and the substrate. Since the nanowire current limiter is fabricated directly underneath each field emitter, we maintain an emitter density of 10⁸ emitters/cm², enabling high current density. The design of the anode prevents tip erosion from back-streaming ions. These arrays demonstrate consistent current scaling of array sizes from a single emitter to 25,000 emitters, low voltage (VGE < 60V), high current density (J > 100 A/cm² ), and long lifetime (t > 100 hours at 100 A/cm² , > 100 hours at 10 A/cm² , and > 300 hours at 100 mA/cm²). The current density enabled by our device structure is an improvement of > 10x over state-of-the art (~~ 1 - 10 A/cm²) for Si field emission cathodes operated in a direct current mode. Our devices demonstrated a turn-on voltage as low as 8.5 V. This low-voltage enabled operation in a 500 Torr He ambient with an anode-emitter voltage below the first ionization potential of He (~ 19 V). These high current, high current density, long lifetime cold cathodes could enable new approaches to x-ray imagers, RF amplifiers, THz sources, and deep UV sources.en_US
dc.description.statementofresponsibilityby Stephen Angelo Guerrera.en_US
dc.format.extent241 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleHighly scaled silicon field emitter arrays with integrated silicon nanowire current limitersen_US
dc.typeThesisen_US
dc.description.degreePh. D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.identifier.oclc953416738en_US


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