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dc.contributor.advisorCharles G. Sodini, Jeremy Walker, and Andrew Lewine.en_US
dc.contributor.authorKakuru, George Bamuturakien_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2016-12-22T15:17:57Z
dc.date.available2016-12-22T15:17:57Z
dc.date.copyright2016en_US
dc.date.issued2016en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/105997
dc.descriptionThesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.en_US
dc.descriptionThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.en_US
dc.descriptionCataloged from student-submitted PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 81-82).en_US
dc.description.abstractAs devices continue to scale, Process, Voltage and Temperature (PVT) variations tend to have a bigger impact on circuit performance. The ability to measure this impact provides essential knowledge about the circuit's current performance and opens the door to compensation techniques. Off-chip measurement circuits are usually of limited bandwidth and load the measured circuit, thus affecting the measurement result. Onchip circuits on the other hand have the potential for high bandwidth and, if designed well, have small area and can be incorporated into different parts of the chip. For this project a delay and temperature measurement circuit is designed. The delay measurement circuit relies on a method called Code Density Test (CDT), a statistical method which involves counting the number of asynchronous edges that occur within the relative delay of two synchronous clocks. The temperature measurement circuit converts temperature to a delay which can then be measured by the CDT circuit.en_US
dc.description.statementofresponsibilityby George Bamuturaki Kakuru.en_US
dc.format.extent82 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleDesign of on-chip monitoring circuits for clock delay and temperatureen_US
dc.typeThesisen_US
dc.description.degreeM. Eng.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc965798463en_US


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