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dc.contributor.advisorDavid J. Perreault.en_US
dc.contributor.authorAlShehab, Ali Saeeden_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2016-12-22T16:27:58Z
dc.date.available2016-12-22T16:27:58Z
dc.date.copyright2010en_US
dc.date.issued2015en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/106076
dc.descriptionThesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.en_US
dc.descriptionCataloged from PDF version of thesis. "September 2015."en_US
dc.descriptionIncludes bibliographical references (pages 83-85).en_US
dc.description.abstractThis thesis explores the design of power converters that deliver isolated low-voltage dc output (~24V) and operate from "universal" ac input voltage (85 - 264 Vac RMS). It is important that these converters have good overall efficiency (~90-95%), and good ac line power factor (>0.9, and ideally >0.95) to better utilize the available energy. This thesis looks into achieving high efficiency, high power factor, low voltage stresses, and smaller component sizes by utilizing high frequency operation. The research focuses on component and subsystem evaluation, development and testing as a part of many-person research in this space. The thesis presents a literature based study on current PFC circuit designs and tradeoffs. It also introduces a specific PFC architecture, which provides a low dc output voltage drawing energy from a wide range ac input voltage while maintaining a high power factor. The architecture includes two stages: The first is a "Power Factor Correction" (PFC) which functions as an input stage drawing energy from a wide-range input current. It uses a resonant transition inverted (RTI) buck converter topology to step down the voltage from line voltage (85 - 264 Vac RMS) to around 72V. Furthermore, the inductor for the RTI buck is analyzed. The middle stage is an energy buffer to provide the required energy level for twice line frequency energy buffering and 20ms of energy hold up. The capacitor requirements, analysis, and selection are explored and developed. The second stage is a transformation and regulation stage which also provides electrical isolation between the ac input and dc output. The thesis also explores the use of available conventional high-density telecom "brick" converters as a second stage. In conclusion, the project explores the possibility of using a buck configuration for the PFC, sacrificing the ability to use high energy density 400V capacitors while gaining the advantage of using the high-density telecom brick converters and different output voltage options.en_US
dc.description.statementofresponsibilityby Ali Saeed AlShehab.en_US
dc.format.extent95 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleDevelopment and analysis of high-frequency, high-density PFC power conversionen_US
dc.typeThesisen_US
dc.description.degreeM. Eng.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc965198141en_US


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