Reconciling modal and time domain techniques in photonic simulation

Abstract

Three dimensional Finite Difference Time Domain (3D-FDTD) simulation serves as the indisputable gold standard for device design and verification in silicon photonics. However, 3D-FDTD is prohibitively expensive for large devices let alone cascaded systems, leading to the pursuit of a diversified simulation toolkit to acquire the full device response or combined device (cascade or parallel) response. A modular approach is followed subsequently. For analyzing silicon photonics at the systems level, transfer matrices in the modal/frequency domain are ubiquitously used. These matrices encapsulate the frequency response as well as the coupling coefficients between the various optical eigenmodes across all device ports. In this thesis we formulate and explore the performance of a fast, memory efficient stand-alone FDTD based algorithm that uses transfer matrices within the simulation window for the optical characterization of adiabatic mode-evolution devices. This class of adiabatic devices is vital to silicon photonics systems thanks to their broadband nature and reliable performance under fabrication induced perturbations and parameter variation. In our approach, the simulation domain is divided into blocks which can be simulated independently in the time domain, and then combined using modal transfer matrices. It is critical that we can match the accuracy of a 3D-FDTD simulation for a base class of devices and make an argument that time domain and modal techniques can be perfectly reconciled in a simulation environment where these devices appear and play a significant role. This environment might be targeting a particular device or even an entire section of the chip. When compared to pure 3D-FDTD this approach proves auspicious from a computational standpoint as it yields, in the limit of large devices, an asymptotic linear speedup when the blocks are simulated sequentially, and can further yield a quadratic speedup when an extra level of parallelization is employed.