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dc.contributor.advisorJesús A. del Alamo.en_US
dc.contributor.authorGuo, Alexen_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2017-03-10T15:05:53Z
dc.date.available2017-03-10T15:05:53Z
dc.date.copyright2016en_US
dc.date.issued2016en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/107335
dc.descriptionThesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.en_US
dc.descriptionCataloged from PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 109-116).en_US
dc.description.abstractGaN is a promising alternative to Si for transistors for power electronics. For high-voltage applications, the GaN high electron mobility transistor with insulated gate (MIS-HEMT) is an attractive transistor structure because of its high breakdown voltage combined with low gate leakage current. Impressive device performance has recently been reported. However, before GaN MIS-HEMTs cab be deployed in the field, reliability and stability issues need to be solved. In particular, the threshold voltage (VT) instability under high voltage and temperature stress, sometimes referred to as bias-temperature instability (BTI), is a serious concern. The physical mechanisms responsible for BTI in GaN MIS-HEMT are not well understood. This is mainly because of the complex gate stack with multiple layers and interfaces, which presents many trapping sites with complex dynamics. In this work, a simpler GaN MOSFET structure is used to isolate the role of the gate oxide and the oxide/GaN interface in BTI. Using a carefully designed benign characterization approach, we have studied in detail the response to positive and negative gate bias stress of GaN MOSFETs with various gate dielectrics. This has allowed us to postulate relevant physical mechanisms. For positive gate stress (PBTI), positive VT shifts are caused by a combination of electron trapping in pre-existing oxide traps and trap generation either at the oxide/GaN interface (SiO₂/GaN) or in the oxide close to the interface (A1₂O₃/GaN). For negative gate stress (NBTI), three degradation mechanisms are proposed. In low-stress regime, recoverable electron detrapping from pre-existing oxide traps takes place resulting a temporary negative VT shift. In mid-stress regime, a transient positive VT shift is probably caused by electron trapping in the GaN channel under the edges of the gate. In high-stress regime, there is a permanent negative VT shift, which is consistent with interface state generation. In addition, we have confirmed that for benign positive and negative gate bias stress, there is a unified reversible mechanism that accounts for the device dynamics and that is electron trapping/detrapping in pre-existing oxide traps. This work provides fundamental understanding to elucidate the reliability and instability of high-voltage GaN MIS-HEMTs.en_US
dc.description.statementofresponsibilityby Alex Guo.en_US
dc.format.extent116 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsMIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleBias temperature instability (BTI) in GaN MOSFETsen_US
dc.typeThesisen_US
dc.description.degreePh. D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc972904520en_US


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