Prospects of germanium-based MOSFETs and tunnel transistors for low power digital logic

Abstract

Moore's law has driven technological improvements for decades by halving the areal footprint of the transistor every two years and increasing the performance of making integrated circuits while reducing their cost. The ability to reduce the footprint of the device was enabled by advances in processing technology, novel materials and device design. As ever-smaller footprints are desired, power density limitations and performance degradation require more innovations on all fronts. Recently introduced improvements to integrated circuits are high-K and metal gate for MOSFETs (45-nm node onward), the FinFET (22-nm node onward) and air gaps between copper interconnects (14-nm node) illustrating that at every new technology node there needs to be a materials or process-related improvement to reduce power and maintain performance. Other approaches are also being explored or taken to further improve the MOSFET performance in future technology nodes, namely use of channel materials with higher carrier mobility such as SiGe and Ge for p-MOSFETs, III-V compound semiconductors for n-MOSFETs and steep subthreshold swing devices such as tunnel field effect transistors (TFETs). This work evaluates both approaches utilizing germanium (Ge) and strained-Ge as a material to understand the benefits and drawbacks to both approaches. Hypothetically, high carrier mobility and velocity channel materials can lower the overall power consumption because lower power supply voltage is required to obtain the same amount of current. Germanium and strained-Ge are candidates for the channel material of p-MOSFETs. MOSFETs made using Ge and strained-Ge as the channel material are evaluated based upon the ITRS roadmap requirements using experimental results in this work and data from literature. The approach for using TFETs was evaluated in this work also using germanium as a channel material. TFETs can have a steep subthreshold swing (SS), better than the minimum of 60 mV/decade at room temperature for a MOSFET, which also reduces the total power and supply voltage required for operation. The reduced SS is hypothetically achieved through the band-to-band tunneling which allows for the filtering of the Fermi-tail distribution of carriers. Experimentally, TFETs have not generally shown the steeper than Fermi-tail SS promised by the theory and this work uses both results from fabricated strained-Si/strained-Ge TFETs as well as modeling to explain why this has been the case. The challenges for both technologies are outlined in this thesis and suggestions are made on approaches to tackling their respective intrinsic problems from the point of view of Ge-based devices.