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dc.contributor.advisorJesús A. del Alamo.en_US
dc.contributor.authorZhao, Xin, Ph. D. Massachusetts Institute of Technologyen_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Materials Science and Engineering.en_US
dc.date.accessioned2017-09-15T14:21:33Z
dc.date.available2017-09-15T14:21:33Z
dc.date.copyright2017en_US
dc.date.issued2017en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/111256
dc.descriptionThesis: Ph. D., Massachusetts Institute of Technology, Department of Materials Science and Engineering, 2017.en_US
dc.descriptionThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.en_US
dc.descriptionCataloged from student-submitted PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 156-166).en_US
dc.description.abstractCombining the superior carrier transport properties and flexible band structure engineering from III-V materials and ultimate scalability of vertical nanowire (VNW) device architecture, III-V VNW transistors are promising to extend Moore's law further than any other device technology. In this thesis, III-V VNW transistor technology has been pioneered via a top down approach for logic applications in future ultra-low power systems. Process flow and critical modules for sub-10 nm VNW transistors are developed from scratch. A novel dry etch technique based on BCl₃/SiCl₄/Ar chemistry for fabricating sub-20 nm III-V nanostructures with smooth, vertical sidewall and high aspect ratio (> 10) is developed. Digital etch (DE) is shown to mitigate the dry etch damage and reduce NW diameter below 10 nm in a controllable fashion while preserving the sidewall roughness and NW shape. Top-down InGaAs VNW MOSFET is demonstrated for the first time. Record Ion of 224 μA/μm is obtained at Ioff = 100 nA/μm with Vdd = 0.5 V in third generation devices. With novel solvent-based, switching characteristics are observed in devices with diameter as small as 14 nm. The impact of the intrinsic source/drain asymmetry on the device electrical characteristics is studied in detail, highlighting the importance of uniform NW diameter. The first experimental demonstration of III-V VNW TFETs with an InGaAs/InAs heterojunction fabricated by a top-down approach is introduced. Second generation TFETs demonstrate sub-thermal subthreshold characteristics over two orders of magnitude of current and a record high I60 in any experimental TFETs for Vds < 1 V at the time of device fabrication. The comparison of two generations of TFETs confirms oxide/semiconductor interface trapassisted tunneling as the source of significant temperature dependence in the first device generation. Detailed analysis on the conductance-voltage characteristics on both generations of devices reveal a 100-120 mV/dec steepness of Urbach tails in the VNW TFETs.en_US
dc.description.statementofresponsibilityby Xin Zhao.en_US
dc.format.extent166 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsMIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectMaterials Science and Engineering.en_US
dc.titleIII-V vertical nanowire transistor for ultra-low power applicationsen_US
dc.typeThesisen_US
dc.description.degreePh. D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Materials Science and Engineering.en_US
dc.identifier.oclc1003290886en_US


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