MIT Libraries logoDSpace@MIT

MIT
View Item 
  • DSpace@MIT Home
  • MIT Libraries
  • MIT Theses
  • Doctoral Theses
  • View Item
  • DSpace@MIT Home
  • MIT Libraries
  • MIT Theses
  • Doctoral Theses
  • View Item
JavaScript is disabled for your browser. Some features of this site may not work without it.

Automatic application-specific optimizations under FPGA memory abstractions

Author(s)
Yang, Hsin-Jung
Thumbnail
DownloadFull printable version (28.71Mb)
Other Contributors
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Advisor
Srinivas Devadas and Joel Emer.
Terms of use
MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission. http://dspace.mit.edu/handle/1721.1/7582
Metadata
Show full item record
Abstract
FPGA-based accelerators have great potential to achieve better performance and energy-efficiency compared to general-purpose solutions because FPGAs permit the tailoring of hardware to a particular application. This hardware malleability extends to FPGA memory systems: unlike conventional processors, in which the memory system is fixed at design time, cache algorithms and network topologies of FPGA memory hierarchies may all be tuned to improve application performance. As FPGAs have grown in size and capacity, FPGA physical memories have become richer and more diverse in order to support the increased computational capacity of FPGA fabrics. Using these resources, and using them well, has become commensurately more difficult, especially in the context of legacy designs ported from smaller, simpler FPGA systems. This growing complexity necessitates automated build procedures that can make good use of memory resources by performing resource-aware, application-specific optimizations. In this thesis, we leverage the freedom of abstraction to build program-optimized memory hierarchies on behalf of the user, making FPGA programming easier and more efficient. To enable better generation of these memory hierarchies, we first provide a set of easy-to-use memory abstractions and perform several optimization mechanisms under the abstractions to construct various memory building blocks with different performance and cost tradeoffs. Then, we introduce a program introspection mechanism to analyze the runtime memory access characteristics of a given application. Finally, we propose a feedback-directed memory compiler that automatically synthesizes customized memory hierarchies tailored for different FPGA applications and platforms, enabling user programs to take advantage of the increasing memory capabilities of modern FPGAs.
Description
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.
 
Cataloged from PDF version of thesis.
 
Includes bibliographical references (pages 159-167).
 
Date issued
2017
URI
http://hdl.handle.net/1721.1/112034
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.

Collections
  • Doctoral Theses

Browse

All of DSpaceCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CollectionBy Issue DateAuthorsTitlesSubjects

My Account

Login

Statistics

OA StatisticsStatistics by CountryStatistics by Department
MIT Libraries
PrivacyPermissionsAccessibilityContact us
MIT
Content created by the MIT Libraries, CC BY-NC unless otherwise noted. Notify us about copyright concerns.