Dielectric spin coating characterization, modeling, and planarization using fill patterns for advanced packaging technologies

Abstract

Redistribution layers (RDLs) are separate packaging layers dedicated to connecting dies with each other, and to external I/O ports in advanced 2.5D packaging technologies. These layers can be made smaller than the bulky metal traces in conventional substrate packaging, reducing electrical delay and power consumption. Currently, the damascene process is the most common method to create the copper traces in RDLs. However, due to the required inclusion of chemical mechanical polishing (CMP), this process is significantly more expensive than semi-additive electrochemical plating (ECP) and dielectric spin-coating (DSC) processes. The semi-additive techniques are typically avoided as, without CMP, they suffer from thickness variations following the fabrication of each layer. As multiple layers are fabricated, these variations compound, and can result in a structure with significant topographical and electrical performance concerns. In this thesis, we model and predict the surface non-uniformities resulting from the DSC process applied to underlying topographies, and propose dummy fill and cheesing patterns which control the variations of the DSC process. We first design test vehicles (TVs) which represent topographies common in RDLs, most notably the copper lines and vias, and use these to experimentally determine the thickness variations caused by each process. We then develop empirical models based on these results. The DSC process is modeled as a convolution between the underlying topography (typically the copper lines) and an appropriately chosen impulse response. Finally, we present dummy fill and cheesing patterns that have the potential to control the variations of both processes for any arbitrary layout.