Designing fast and programmable routers
Author(s)Sivaraman Kaushalram, Anirudh
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Hari Balakrishnan and Mohammad Alizadeh.
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Historically, the evolution of network routers was driven primarily by performance. Recently, owing to the need for better control over network operations and the constant demand for new features, programmability of routers has become as important as performance. However, today's fastest routers, which have 10-100 ports each running at a line rate of 10-100 Gbit/s, use fixed-function hardware, which cannot be modified after deployment. This dissertation describes three router hardware primitives and their corresponding software programming models that allow network operators to program specific classes of router functionality on such fast routers. First, we develop a system for programming stateful packet-processing algorithms such as algorithms for in-network congestion control, buffer management, and data-plane traffic engineering. The challenge here is the fact that these algorithms maintain and update state on the router. We develop a small but expressive instruction set for state manipulation on fast routers. We then expose this to the programmer through a high-level programming model and compiler. Second, we develop a system to program packet scheduling: the task of picking which packet to transmit next on a link. Our main contribution here is the finding that many packet scheduling algorithms can be programmed using one simple idea: a priority queue of packets in hardware coupled with a software program to assign each packet's priority in this queue. Third, we develop a system for programmable and scalable measurement of network statistics. Our goal is to allow programmers to flexibly define what they want to measure for each flow and scale to a large number of flows. We formalize a class of statistics that permit a scalable implementation and show that it includes many useful statistics (e.g., moving averages and counters). These systems show that it is possible to program several packet-processing functions at speeds approaching today's fastest routers. Based on these systems, we distill two lessons for designing fast and programmable routers in the future. First, specialized designs that program only specific classes of router functionality improve packet processing throughput by 10-100x relative to a general-purpose solution. Second, joint design of hardware and software provides us with more leverage relative to designing only one of them while keeping the other fixed.
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student-submitted PDF version of thesis.Includes bibliographical references (pages 141-155).
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.; Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.