Cost benefit analysis of process change implementation : alternate wet cleaning technology in the semiconductor manufacturing industry

Abstract

Maintaining wafer surfaces free of contamination is an essential requirement for the successful fabrication of semiconductor devices. With the growing trend of increased device complexity and reduction of device feature sizes, the area of wet cleaning of substrate surfaces has gained importance. The existence of organic and metallic contaminant particles and thin films on a wafer surface can drastically reduce line yield. Recent improvements in wet cleaning technology have presented alternate wafer cleaning techniques. The J.T. Baker clean process is a two step replacement for the four step RCA clean which is the current industry standard. The J.T. Baker clean process involves a significant reduction in chemical costs, process time, volume of disposed effluent, and parts usage. Furthermore, the J.T. Baker clean process eliminates the use of environmentally hazardous chemicals such as hydrochloric acid and ammonium hydroxide. However, process change in high volume semiconductor manufacturing facilities presents high levels of risk. A cost benefit model can be used to clearly outline the potential cost benefits and risks associated with implementing a process change in the semiconductor manufacturing facility. Only after understanding the risks involved and having a clear sense of the potential for financial gain can an informed decision on process change be made. This study used the Intel Fab 12 fabrication facility in Chandler, Arizona as a case study to model cost benefits and risk factors associated with implementing the J.T. Baker clean process. It was found that an expected value of cost savings of $285,000 per year could be achieved by replacing the RCA clean method with the J.T. Baker clean process.