Design-space and scalable technology for GaN based power transistors

Abstract

As silicon devices approach their intrinsic material and technological limit, there is an opportunity for alternative semiconductor materials to push the performance of electronics forward. Gallium nitride (GaN) has demonstrated very promising performance for advanced electronics, but there is still room for improvement. This thesis discusses several new transistor designs to improve the performance of GaN-based power devices as well as demonstrations of their scaling potential and integration capability with silicon. Specifically, we have developed a wide-periphery GaN fin-based high electron mobility transistor process for power switching. The process was developed with emphasis on the passivation, field plates, gate periphery scaling, and packaging. A CMOS compatible GaN processing technology on 200-mm wafers was developed and optimized, with particular attention focused on the recess etching through the wide-bandgap AlGaN barrier to reduce the contact resistance. A study of a heterogeneous integration technology to integrate GaN and Si devices was conducted. This involved an approach to monolithically integrate GaN and Si devices which used a bonded SOI wafer with a Si (111) substrate and Si (100) device layer with windows opened to access the (111) layer to selectively grow GaN. Characterization of the transistor properties in GaN windows of different sizes was performed to qualify the optimal window size for power devices in future integrated systems.