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Flexible and solution-processed organic thin film transistors for high voltage applications

Author(s)
Shih, Andy
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Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Advisor
Akintunde Ibitayo Akinwande.
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MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission. http://dspace.mit.edu/handle/1721.1/7582
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Abstract
6,13-Bis(triisopropylsilylethynyl)pentacene and pentacene high-voltage organic thin film transistors (HVOTFTs) were fabricated on solid and flexible substrates via a low temperature (< 120 °C) solution-processed and vacuum-deposited fabrication methods, achieving breakdown voltages and on/off current ratios beyond -550 V and 10⁶ A/A, respectively, a first of its kind. The HVOTFT design was based on a dual channel architecture, where a gated region enabled FET capabilities and an offset region accommodated the high-voltage. An HVOTFT capable of driving high-voltages ([V[lower case DS]] > 100 V) while being controlled by a relatively low gate-to-source voltage ([V[lower case GS]] < 50 V) will enable new applications on arbitrary and flexible substrates, such as large electrostatic MEMS actuators, electroactive polymers, novel displays, field-emitter arrays for digital x-ray imaging as well as photovoltaic systems on glass. A high-k dielectric Bi₁.₅Zn₁Nb₁.₅O₇ and a low-k organic dielectric parylene-C were incorporated into the HVOTFT process to improve threshold voltage and mobility. Field plate designs and self-assembled monolayers were also explored to enhance the HVOTFT's electrical characteristics by directly controlling the charge carrier distribution within the channel or by improving the charge carrier injection into the organic semiconductor. Moreover, a self-shearing drop cast deposition method has been employed for the HVOTFT for the first time, growing large and highly oriented organic semiconductor grains. Solution-processing will enable room-temperature, air ambient and large-area depositions techniques, reducing fabrication overhead. Furthermore, a self-aligned solution-processing method based on surface energy engineering was developed with self-assembled monolayers to create pre-patterned organic semiconductor channels without the need for etching.
Description
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.
 
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
 
Cataloged student-submitted from PDF version of thesis.
 
Includes bibliographical references (pages 257-270).
 
Date issued
2018
URI
http://hdl.handle.net/1721.1/117842
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.

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