Energy efficient computing : from nanotubes to negative capacitance

Abstract

Physical scaling of silicon-based field-effect transistors (FETs) has been a major driving force to improve computing energy efficiency (quantified by the energy-delay product, EDP, the product of energy consumption and circuit delay) for decades. However, continued silicon scaling is becoming increasingly challenging. This is motivating the search for beyond-silicon nanotechnologies, such as one-dimensional carbon nanotubes (CNTs) or two-dimensional nanomaterials such as transition metal dichalcogenides (TMDs) or black phosphorous. Yet simply relying on new materials alone is insufficient for realizing the next generation of energy-efficient computing. Rather, coordinated advances across several disciplines are required, as their combined benefits are greater than the sum of their individual benefits. In this work, I illustrate how by combining multiple advances - from new device physics to new nanomaterials to new device geometries - there is a feasible path towards realizing over an order of magnitude benefit is energy efficiency for digital very-large-scale integrated (VLSI) systems. As a case study, this thesis focuses on CNT-based electronics. I experimentally demonstrate that by leveraging this new nanomaterial, we can naturally realize CNT field-effect transistors (CNFETs) that both take advantage of new device physics (specifically, negative capacitance), as well as new device geometries (specifically, back-gate geometries). Yet despite this potential, there is a major challenge: while new nanomaterials introduce many new opportunities (as mentioned above), they simultaneously introduce many challenges. For instance, CNFETs are unfortunately often subject to substantial off-state leakage current (/OFF) which results in increased leakage power and potential incorrect logic functionality. Therefore, to realize the potential benefits of these new nanomaterials (and the new opportunities they enable), practical obstacles must be overcome. Within this thesis, we demonstrate a path for mitigating this leakage by engineering back-gate CNFET geometries with asymmetric gates (e.g., gates that overlap the source but not the drain). The key contributions of this thesis are the following: 1. We experimentally fabricate the world's most-scaled CNFETs that fit within a contacted gate pitch (CGP, a key metric determining the area of a FET) of 30 nm, suitable for sub-3nm technology nodes. This is enabled by exploiting back-gate FET geometries, which are naturally enabled by the unique low-temperature processing of CNFETs. 2. We use the CNFETs above to realize cascadable digital logic that fit within a world record CGP of 30 nm. This is the most scaled digital logic realized to-date. 3. We perform the first rigorous analysis of back-gate FET geometries, and show for digital VLSI circuits that in addition to scaling benefits, back-gate CNFETs improve EDP by 1.6x vs. top-gate CNFETs and 2.2x vs. gate-all-around CNFETs. 4. First experimental demonstration of Negative Capacitance CNFETs (NC-CNFETs), combining the benefits of CNTs, back-gate geometries, and new physics (negative capacitance ferroelectrics). 5. Experimentally reveal the underlying cause behind excess off-state leakage current in CNFETs, and demonstrate a path for overcoming it (leveraging the same back-gate FET geometries used for contributions 1-4). We experimentally implement our approach on CNFETs fabricated across wide range of technology nodes (from 180 nm node to >1 [mu] node), and show a >60x improvement in off-state leakage current in CNFETs.