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dc.contributor.advisorJames Fitzpatrick and Yury Polyanskiy.en_US
dc.contributor.authorAl Ai Baky, Mohammed (Mohammed M.)en_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2018-12-18T19:47:55Z
dc.date.available2018-12-18T19:47:55Z
dc.date.copyright2018en_US
dc.date.issued2018en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/119738
dc.descriptionThesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.en_US
dc.descriptionThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.en_US
dc.descriptionCataloged from student-submitted PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 65-67).en_US
dc.description.abstractFlash memory companies are increasing the number of bits per cell to obtain higher information capacity per cell, starting from 1 bit/cell and going to 4 bits/cell recently. This scaling is enabled by the advancements in flash semiconductor technology, specifically the Bit Cost Scalable (BiCS) technology. However, capacity per cell scaling comes with performance, reliability, and endurance challenges. The industry has only used integer number of bits per cell, which makes the tradeoff between the capacity and the other system features less flexible than using fractional bits. This project explores programming 13 levels of charge ( 3.7 bits) into a QLC flash cell that normally carries 16 levels of charge (4 bits). We evaluate the 13-ary scheme against the 16-ary one and we show that the 13-ary has the same reliability at a lower SNR as the 16-ary, or the 13-ary has higher reliability than the 16-ary at the same SNR. We design binary and non-binary Quasi-Cyclic LDPC codes and implement Belief Propagation decoders for them.en_US
dc.description.statementofresponsibilityby Mohammed Al Ai Baky.en_US
dc.format.extent67 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsMIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titlePrime-sized multilevel flash memory with non-binary LDPCen_US
dc.typeThesisen_US
dc.description.degreeM. Eng.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc1078689336en_US


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