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dc.contributor.advisorArvind and Beth Markey.en_US
dc.contributor.authorRodriguez Gallegos, Juan Miguelen_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2018-12-18T20:04:03Z
dc.date.available2018-12-18T20:04:03Z
dc.date.copyright2018en_US
dc.date.issued2018en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/119773
dc.descriptionThesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.en_US
dc.descriptionCataloged from PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 32-33).en_US
dc.description.abstractThe hardware verification pipeline for server-scale system on chips (SoCs) is as complex as the SoCs themselves. Intel's Validation Acceleration through Shared Expertise (VASE) tool allows teams at different stages of the verification pipeline-from subsystem development to system integration-to share key architectural, test, and debug knowledge. By enabling system experts to automate the detection of common simulation failures, VASE allows the engineers who are inheriting a subsystem to instantly have access to their expertise whenever a simulation failure occurs. The VASE tool has the potential to greatly increase validation efficiency, but its adoption into Intel's verification work flow is put at risk by usability issues. To address these shortcomings, I developed a user interface that facilitates the creation of the simulation failure debug decision trees by the system experts. This GUI aims to increase usability for tree definition and manipulation, to enforce node subtree coherence across all trees, and to provide a tree building solution which scales with the complexity of the system.en_US
dc.description.statementofresponsibilityby Juan Miguel Rodriguez Gallegos.en_US
dc.format.extent33 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsMIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleA user interface for algorithmic debugen_US
dc.typeThesisen_US
dc.description.degreeM. Eng.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc1078637854en_US


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