dc.contributor.advisor | David D. Clark. | en_US |
dc.contributor.author | Ndiaye, Oumar, 1966- | en_US |
dc.date.accessioned | 2005-08-16T21:58:20Z | |
dc.date.available | 2005-08-16T21:58:20Z | |
dc.date.copyright | 1994 | en_US |
dc.date.issued | 1994 | en_US |
dc.identifier.uri | http://hdl.handle.net/1721.1/12024 | |
dc.description | Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994. | en_US |
dc.description | Includes bibliographical references (p. 77-78). | en_US |
dc.description.statementofresponsibility | by Oumar Ndiaye. | en_US |
dc.format.extent | 78 p. | en_US |
dc.format.extent | 4236426 bytes | |
dc.format.extent | 4236187 bytes | |
dc.format.mimetype | application/pdf | |
dc.format.mimetype | application/pdf | |
dc.language.iso | eng | en_US |
dc.publisher | Massachusetts Institute of Technology | en_US |
dc.rights | M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. | en_US |
dc.rights.uri | http://dspace.mit.edu/handle/1721.1/7582 | |
dc.subject | Electrical Engineering and Computer Science | en_US |
dc.title | An efficient implementation of a hierarchitcal weighted fair queue packet scheduler | en_US |
dc.type | Thesis | en_US |
dc.description.degree | M.S. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | |
dc.identifier.oclc | 31311540 | en_US |