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dc.contributor.advisorAdam Chlipala.en_US
dc.contributor.authorDuxovni, Faye(Faye Samara)en_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2019-09-11T21:55:20Z
dc.date.available2019-09-11T21:55:20Z
dc.date.copyright2018en_US
dc.date.issued2018en_US
dc.identifier.urihttps://hdl.handle.net/1721.1/122053
dc.descriptionThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.en_US
dc.descriptionThesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018en_US
dc.descriptionCataloged from student-submitted PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 47-48).en_US
dc.description.abstractA recurring problem in cryptography engineering is the potential for secret data to be leaked through aspects of software and hardware that are orthogonal to functional correctness. In particular, much effort is put into writing cryptography code whose timing behavior - how many CPU clock cycles it takes to complete a given cryptographic operation - is independent of any secret inputs to that operation. This is a difficult problem because it depends not only on the code itself, but also on various optimizations such as branch prediction and memory caching implemented by the underlying hardware the program runs on. We make use of Kami, a domain-specific language for describing and formally verifying hardware modules, to build a system for constructing machine-checked proofs that a given piece of code running on a given RISC-V CPU design will not leak secret inputs through timing behavior. Our system allows software and hardware to be analyzed and verified independently, and we prove that any combination of software and hardware that meet our validation criteria will be safe from timing-based side channels. We demonstrate an example of validating a real cryptographic program and a concrete RISC-V CPU using our system, illustrating the applicability of our tools and laying the groundwork for validating more complex programs and CPUs.en_US
dc.description.statementofresponsibilityby Faye Duxovni.en_US
dc.format.extent48 pages ;en_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsMIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleMechanized proofs that hardware is safe from timing attacksen_US
dc.typeThesisen_US
dc.description.degreeM. Eng.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.identifier.oclc1108621497en_US
dc.description.collectionM.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Scienceen_US
dspace.imported2019-09-11T21:55:20Zen_US
mit.thesis.degreeMasteren_US
mit.thesis.departmentEECSen_US


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