Three-dimensional device and circuit architectures : new systems with new nanotechnologies

Abstract

Physical scaling of silicon-based field-effect transistors (FETs) has been a major driving force to improve computing energy efficiency (quantified by the energy-delay product, EDP, the product of energy consumption and circuit delay) for decades. However, continued silicon scaling is becoming increasingly challenging. This is motivating the search for beyond-silicon nanotechnologies, such as one-dimensional carbon nanotubes (CNTs) or two-dimensional nanomaterials such as transition metal dichalcogenides (TMDs). Yet simply relying on new materials alone is insufficient for realizing the next generation of energy-efficient computing. Rather, coordinated advances across the entire computing system stack are required, as their combined benefits are greater than the sum of their individual benefits.

In this work, I illustrate how by combining multiple advances - from new nanomaterials to new device geometries to new circuit architectures - there is a feasible and exciting path towards realizing the next generation of energy efficiency for digital very-large-scale integrated (VLSI) systems. As a case study, this thesis focuses on CNT-based electronics. I experimentally demonstrate that by leveraging this new nanomaterial, we can naturally realize CNT field-effect transistors (CNFETs) that take advantage of new device geometries (specifically, new three-dimensional (3D) stacked-channel transistor geometries), as well as new 3D integration schemes (specifically, 3D circuit architectures based on stacked-channel transistors and new schemes for monolithic 3D heterogeneous integration of a wide range of technologies spanning silicon, III-V, and CNTs). The key contributions of this thesis are the following: 1. We experimentally demonstrate, DISC-FETs (Dual Independent Stacked Channel Field-Effect Transistors), a new 3D transistor architecture naturally enabled by CNFETs low temperature processing requirements.

2. We use this new 3D transistor architecture to enable new 3D circuit layouts, providing a promising path for energy-and area-efficient very-large scaled integrated (VLSI) circuits. 3. We develop and experimentally realize X3D, a new paradigm for monolithic 3D heterogeneous integration of a wide range of nanowire-based semiconductors (e.g. silicon, III-V, and CNTs), enabling new system design that leverages a range of technologies for a range of different functionality - all within the same chip (wide-bandgap III-Vs for power management, CNTs for energy efficiency, tailored bandgaps for specialized sensors or imagers, etc.). 4. We leverage X3D to experimentally realize digital logic spanning multiple vertical circuit layers and heterogeneous nanowire-based semiconductors.