InGaAs MOSFETs for logic and RF applications : reliability, scalability and transport studies
Author(s)Cai, Xiaowei,Ph.D.Massachusetts Institute of Technology.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Jesús A. del Alamo.
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InGaAs has emerged as an extraordinary n-channel material due to its superb electron transport properties and low voltage operation. With tremendous advancements over the years, InGaAs MOSFETs have attracted much attention as promising device candidates for both logic and THz applications. However, many challenges remain. This thesis addresses some of the critical issues facing InGaAs MOSFETs and advances the understanding of the limiting factors confronting InGaAs MOSFET technology. First, it identifies a new instability mechanism in self-aligned InGaAs MOSFETs caused by fluorine migration and passivation of Si dopants in n-InAlAs. This problem is successfully mitigated by eliminating n-InAlAs from the device structure. The new device design achieves improved stability and record device performance. Second, it evaluates the impact of oxide trapping in InGaAs MOSFETs.A comprehensive PBTI study shows that oxide trapping deteriorates device stability, resulting in threshold voltage shifts and degraded device performance. In addition, oxide trapping also compromises DC device performance. High frequency and fast pulse measurements reveal a rich spectrum of oxide traps with different capture/emission times. Furthermore, oxide trapping also complicates the extraction of fundamental parameters in InGaAs MOSFETs and leads to an underestimation of channel mobility. Thus, a new method has been developed, immune to the impact of oxide traps, to evaluate the intrinsic charge-control relationship of the device, and accurately estimate mobility. Thirdly, this thesis re-evaluates the impact of channel scaling on device performance and transport in InGaAs planar MOSFETs and FinFETs. In both cases, mobility degradation with channel thickness or fin width scaling is observed to be much less than suggested by conventional CV methods.When the impact of oxide trapping is avoided, mitigated scaling induced degradation is observed and promising intrinsic transistor performance is revealed. Notably, InGaAs FinFETs exhibit g[subscript m,max] at 1 GHz competitive with current Silicon FinFET technology and high mobility even in very narrow fins ([mu][subscript peak] ~ 570 cm²/V·s at W[subscript f] = 7 nm). This thesis highlights the importance of mitigating oxide trapping. Further, in light of the results obtained here, the prospects of InGaAs MOSFET technology merit a reassessment.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019Cataloged from student-submitted PDF version of thesis.Includes bibliographical references (pages 133-141).
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.