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dc.contributor.advisorTomás Palacios.en_US
dc.contributor.authorZubair, Ahmad,Ph.D.Massachusetts Institute of Technology.en_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2019-11-04T20:22:10Z
dc.date.available2019-11-04T20:22:10Z
dc.date.copyright2019en_US
dc.date.issued2019en_US
dc.identifier.urihttps://hdl.handle.net/1721.1/122744
dc.descriptionThesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019en_US
dc.descriptionCataloged from PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 208-221).en_US
dc.description.abstractSi CMOS technology is approaching its limit to meet the demand for future data-intensive energy efficient ubiquitous electronics. Emerging materials (i.e. low dimensional nanomaterials, novel dielectric/ferroelectric materials) show great promise to overcome the limits of the Si CMOS technology for specific applications. This thesis studies the prospects of two different emerging materials system (the atomically thin two-dimensional materials and ferroelectric oxides) in energy efficient electronic devices for future Systems-on-a-Chip (SoC's) applications. As the channel length of transistors has shrunk over the years, short-channel effects have become a major limiting factor to transistor miniaturization. Atomically thin MoS₂ is an ideal semiconductor material for field-effect transistors (FETs) with sub-10-nm channel lengths.en_US
dc.description.abstractWe study the limit of channel length scaling in MoS₂ FET using the semiconducting-to-metallic phase transition of MoS₂ and demonstrate sub-10-nm channel-length transistor fabrication by directed self-assembly patterning of mono- and trilayer MoS₂ Novel device concepts based on quantum mechanical tunneling (i.e. inter-band tunneling, hot electron injection) and two-dimensional materials can overcome some of the limitations of conventional CMOS devices for both low power and high frequency. We demonstrate inter-band tunneling transistors with room temperature negative differential resistance using van der Waals heterostructure for low power applications. Moreover, we show vertical hot electron transistor (HET) utilizing tunneling injection of hot electrons, which may enable operation at frequencies beyond what Si CMOS can provide.en_US
dc.description.abstractThe integration of the a highly conductive ultra-thin (0.3 nm) monolayer graphene with a GaN platform by van der Waals interaction can simultaneously offer both scalability and high performance in ballistic HET. In the last part of the thesis, we discuss how the use of ferroelectric Hf 0₂ with conventional (i.e. Si, GaN, InGaAs) semiconductor as well as two-dimensional materials systems offers a new degree of freedom when designing novel electronic devices. We demonstrate that the integration of ferroelectric Hf0₂ can enable ultra-low power (MoS₂ FET with subthreshold swing less than 60 mV/decade) as well as, potentially, higher operating frequencies. Finally, we present a proposal for a new analog synaptic device using ferroelectric Hf0₂ for in-memory computation in future SoC platforms.en_US
dc.description.statementofresponsibilityby Ahmad Zubair.en_US
dc.format.extent221 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsMIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleTunneling and ferroelectric based transistors for energy efficient electronicsen_US
dc.typeThesisen_US
dc.description.degreePh. D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.identifier.oclc1124763417en_US
dc.description.collectionPh.D. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Scienceen_US
dspace.imported2019-11-04T20:22:09Zen_US
mit.thesis.degreeDoctoralen_US
mit.thesis.departmentEECSen_US


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