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Virtual wires--overcoming pin limitations in FPGA-based logic emulation

dc.contributor.advisorAnant Agarwal.en_US
dc.contributor.authorBabb, Jonathan Williamen_US
dc.date.accessioned2005-08-16T20:13:22Z
dc.date.available2005-08-16T20:13:22Z
dc.date.copyright1994en_US
dc.date.issued1994en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/12274
dc.descriptionThesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.en_US
dc.descriptionIncludes bibliographical references (p. 99-102).en_US
dc.description.statementofresponsibilityby Jonathan William Babb.en_US
dc.format.extent102 p.en_US
dc.format.extent6213764 bytes
dc.format.extent6213523 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Scienceen_US
dc.titleVirtual wires--overcoming pin limitations in FPGA-based logic emulationen_US
dc.typeThesisen_US
dc.description.degreeM.S.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc30804738en_US


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