Terahertz frequency synthesis in CMOS for a chip-scale molecular clock

Abstract

Clocks are fundamental to modern communications, navigation, and sensing systems. A recently invented chip-scale molecular clock (CSMC) based on terahertz electronics could enable low-cost, atomic-grade timekeeping for applications that are poorly served by existing clock technologies. However, the first CSMC left opportunities to optimize the terahertz electronics for a second version, for instance by improving transmitter phase noise. In this thesis, I designed millimeter-wave and terahertz circuits in CMOS for a new CSMC. A 60GHz VCO, frequency multiplier chain, and terahertz detector were designed for the high-frequency front-end of a 231GHz transceiver. This involved iterative circuit and electromagnetic optimization from schematic to layout. The circuits were integrated with other high-speed and baseband circuits on a single chip in order to synthesize a stable clock signal by locking to the 231.061GHz rotational transition line of carbonyl sulfide (16O 12C 32S) gas. The chip was taped-out in a TSMC 65nm CMOS process and measured. The results offer insights for future work on molecular clocks and terahertz electronics.