Efficient memory and GPU operations for Tiramisu compiler
Efficient memory and graphics processing unit operations for Tiramisu compiler
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Saman P. Amarasinghe.
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The increasing complexity of computer architectures with different memory hierarchies and parallelism characteristics makes generating efficient code a difficult task. Achieving high performance requires complex schedules and data layout transformations which might not be easy to express in a low level language. TIRAMISU  is an optimization framework for generating efficient code for different platforms including CPU, GPU, and distributed systems. It combines the polyhedral intermediate representation with rich scheduling and data layout commands, creating a high level interface to generate high performance code. In this thesis, we present new memory interfaces and GPU operators implemented to extend TIRAMISU compiler. We demonstrate that these features enable users to generate high performance GPU code with concise TIRAMISU programs. We also evaluate TIRAMISU's GPU backend with two benchmarks, matrix multiplication and a recurrent neural network architecture, showing that TIRAMISU outperforms other polyhedral compilers and popular library implementations.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019Cataloged from PDF version of thesis.Includes bibliographical references (pages 59-60).
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.