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Vector-aware space cuts in stencil computations

Author(s)
Ren, Stephanie,M. Eng.Massachusetts Institute of Technology.
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Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Advisor
Tao B. Schardl and Helen Xu.
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MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission. http://dspace.mit.edu/handle/1721.1/7582
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Abstract
This thesis presents work on how cache-efficient serial and parallel stencil computations can be optimized to efficiently use vector instructions on modern general-purpose processors. A stencil computation iteratively updates each point of a d-dimensional grid based on a function of itself and its nearby neighbors. Stencil computations have a wide range of applications from simulation to machine learning, and are often time-intensive. Although a stencil can be computed by repeatedly looping over its d- dimensional grid, previous studies have shown that various parallel and cache-efficient algorithms, including recursive cache-oblivious algorithms, can compute stencils more efficiently. However, these recursive cache-oblivious algorithms can disrupt vectorization and increase the number of instructions required for the computation. Vector-aware space cuts can be used to preserve vectorization in serial and parallel cache-oblivious algorithms for stencil computations, thereby improving their performance. I present improved theoretical analyses of the commonly used and efficient parallel cache-oblivious stencil algorithm due to Frigo and Strumpen to account for vector operations, and we show that vector-aware space cuts improve the asymptotic work -- total computation -- of the algorithm by a factor of the maximum vector width. I present an improved analysis of the algorithm's span -- length of a longest path of dependencies in the computation -- to be O(rhw1 / lg(2(r??1))), where r is the number of trapezoids created in a parallel cut. I show that these theoretical improvements are borne out in practice by demonstrating up to a 1:61 X speed-up in the serial stencil computation and a 1:08 X speed-up in the parallel computation.
Description
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
 
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019
 
Cataloged from student-submitted PDF version of thesis.
 
Includes bibliographical references (pages 71-76).
 
Date issued
2019
URI
https://hdl.handle.net/1721.1/123152
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.

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