Flash analog-to-digital converters with time-based techniques

Abstract

High-speed medium-resolution flash analog-to-digital converters (ADCs) are in high demand in today's wireless and wireline systems. Conventional flash ADCs suffer from limited resolution and high power consumption. This thesis investigates time-based techniques that enhance the performance of a flash ADC at giga-sample-per-second (GS/s) sampling rate. Two major design challenges are addressed in this thesis. The first challenge is the ever-growing comparator offset with the scaling of CMOS technology. Conventional offset calibration methods utilize digitally-controlled capacitor banks or an additional input pair. The disadvantages include slower speed due to the added parasitic capacitance or higher input referred noise due to the extra input transistors. In this thesis, we propose an offset calibration method based on timing skew. The proposed method does not add any extra load to the comparator, avoiding the penalties of conventional methods. The second challenge is the exponentially growing number of comparators with resolution. This thesis proposes a time-based 4x interpolation technique that utilizes the timing information from adjacent comparators to resolve two extra bits of resolution without adding comparators. The number of comparators is reduced to 1/4 of a conventional flash ADC, and calibration capability is provided to achieve an 8-bit accuracy. Both techniques are demonstrated on a prototype flash ADC chip that measures state-of-the-art performances.