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dc.contributor.advisorVivienne Sze and Sertac Karaman.en_US
dc.contributor.authorLi, Peter Zhi Xuan.en_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2020-09-15T21:53:29Z
dc.date.available2020-09-15T21:53:29Z
dc.date.copyright2020en_US
dc.date.issued2020en_US
dc.identifier.urihttps://hdl.handle.net/1721.1/127351
dc.descriptionThesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, May, 2020en_US
dc.descriptionCataloged from the official PDF of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 155-158).en_US
dc.description.abstractExploration problems are fundamental to robotics, arising in various domains, ranging from search and rescue to space exploration. In these domains and beyond, exploration algorithms that allow the robot to rapidly create the map of the unknown environment can reduce the time and energy for the robot to complete its mission. Many eective exploration algorithms rely on the computation of Shannon mutual information (MI) which allow the robot to select the best location to explore in order to gain the most information about the unknown environment. Unfortunately, computing MI metrics is computationally challenging. In fact, a large fraction of the current literature focuses on approximation techniques to devise computationally-efficient algorithms. While the computation of MI can be parallelized and thus computed by many parallel cores, the main challenge that limits throughput is the delivery of data to these cores.en_US
dc.description.abstractAs such, in this work we propose a MI hardware accelerator that has a novel memory banking pattern and an arbiter that ensure eective utilization of all MI cores to maximize throughput. In addition, our rigorous analysis of the banking pattern and arbiter ensures that our designs are near-optimal without resorting to a time-consuming, intuition-based search across a large set of hardware design parameters for verification. Finally, the proposed architecture is validated on an FPGA and implemented on an ASIC in a commercial 65nm technology. Our ASIC implementation computes the MI for an entire map from a real-world experiment of 10.05m x 10.05m at 0.05m resolution in real time at 11Hz, which is 88x and 13x faster than the ARM Cortex-A57 CPU and NVIDIA Pascal GPU on the Jetson TX2 board respectively. Furthermore, the ASIC implementation consumes 162mW, which is 21x lower and 20x lower than the ARM Cortex-A57 CPU and NVIDIA Pascal GPU on the Jetson TX2 board respectively.en_US
dc.description.abstractUsing the entire MI map that is quickly computed by the ASIC, the robot is able to choose the optimal exploration trajectory during path planning such that the amount of exploration time can be reduced during time-critical missions, such as search and rescue.en_US
dc.description.statementofresponsibilityby Peter Zhi Xuan Li.en_US
dc.format.extent158 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsMIT theses may be protected by copyright. Please reuse MIT thesis content according to the MIT Libraries Permissions Policy, which is available through the URL provided.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleHigh-throughput computation of Shannon mutual information on chipen_US
dc.typeThesisen_US
dc.description.degreeS.M.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.identifier.oclc1192486455en_US
dc.description.collectionS.M. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Scienceen_US
dspace.imported2020-09-15T21:53:29Zen_US
mit.thesis.degreeMasteren_US
mit.thesis.departmentEECSen_US


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