A reference model for the PIPE security coprocessor

Abstract

Systematic security solutions implemented at the hardware level offer higher performance than similar software approaches and are harder to attack or bypass. While hardware changes are generally more difficult to integrate into existing systems, the PIPE (Processor Interlocks for Policy Enforcement) coprocessor architecture requires no major changes to the AP (Application Processor) that it runs alongside, which facilitates the integration process. The PIPE provides the ability to enforce a wide variety of security policies utilizing the metadata that it stores for each word of memory and each register on the AP. In this thesis, we define and implement a reference model for the PIPE using the Chisel hardware design language, resulting in an accessible platform for future evaluation and research.