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dc.contributor.advisorJing Kong.en_US
dc.contributor.authorShen, Pin-Chun.en_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2021-01-06T20:17:41Z
dc.date.available2021-01-06T20:17:41Z
dc.date.copyright2020en_US
dc.date.issued2020en_US
dc.identifier.urihttps://hdl.handle.net/1721.1/129307
dc.descriptionThesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, September, 2020en_US
dc.descriptionCataloged from student-submitted PDF of thesis.en_US
dc.descriptionIncludes bibliographical references (pages 204-220).en_US
dc.description.abstractScaling of silicon transistors is reaching its physical limits due to severe short channel effects, threatening to end Moore's law. Advanced beyond-silicon electronic technology requires discoveries of both new channel materials and ultralow-resistance contacts. The aim of this thesis is to develop an understanding of the science and engineering in applying synthetic monolayer semiconductors as the channel materials in field-effect transistors and in achieving excellent electrical contacts to these emerging materials. Monolayer semiconductors such as MoS₂,WS₂ and WSe₂ not only offer atomically thin thicknesses for device minimization, but also embrace desirable physical properties such as dandling-bond-free and atomically flat surface, sizable bandgap, and relatively heavier carrier effective mass to enhance transistor performance at the atomic limit.en_US
dc.description.abstractWe start by developing scalable methods for synthesizing high-quality monolayer MoS₂ that exhibits near intrinsic characteristics and moderate electron mobility at room temperature. These developments improve the fundamental transport property and reduce the unwanted impurity doping of the synthetic monolayer MoS₂ for electronic applications. Next, we further demonstrate a method to eliminate the detrimental defect states in monolayer MoS₂, which mitigates the defect-state induced Fermi-level pinning at the metal-MoS₂ interface. The monolayer MoS₂ transistors fabricated through this technique exhibit a lowered Schottky barrier and a reduced contact resistance at the metal-MoS₂ interface. This study provides an insight into the defect properties of MoS₂ that are fundamentally related to the device performance.en_US
dc.description.abstractFinally, we provide a deeper understanding of the ohmic contact nature at metal-monolayer semiconductor interfaces and propose a new contact paradigm, gap-state saturation, to overcome the in-gap Fermi-level pinning and eventually eliminate the Schottky barrier. We experimentally apply this new ohmic contact technology to a variety of monolayer semiconductors and demonstrate high-performance monolayer semiconductor transistors. We have achieved record-low contact resistance approaching the quantum limit among all the metal-2D semiconductor interfaces. Our monolayer semiconductor transistors have also reached record-high ON-state current density among all the monolayer devices. We show that monolayer semiconductors can have a performance on par with the state-of-the-art silicon-based technology, reaching the goal of next-generation transistor technologies.en_US
dc.description.statementofresponsibilityby Pin-Chun Shen.en_US
dc.format.extent220 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsMIT theses may be protected by copyright. Please reuse MIT thesis content according to the MIT Libraries Permissions Policy, which is available through the URL provided.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleOhmic contact to monolayer semiconductorsen_US
dc.typeThesisen_US
dc.description.degreePh. D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.identifier.oclc1227779042en_US
dc.description.collectionPh.D. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Scienceen_US
dspace.imported2021-01-06T20:17:40Zen_US
mit.thesis.degreeDoctoralen_US
mit.thesis.departmentEECSen_US


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