Scaling trapped-ion quantum computers with CMOS-integrated state readout

Abstract

Quantum information processing (QIP) has emerged as a powerful new computing paradigm as traditional Moore's law scaling slows due to skyrocketing costs of shrinking feature sizes, interconnects becoming the dominant source of energy consumption and delay as transistor critical dimensions fall below 10 nm, and power density limiting the activity factor in digital systems on a chip. Quantum computers use quantum states ("qubits") to store and manipulate information, giving them fundamental performance advantages over classical digital computers in certain applications. Although the feasibility of QIP has been proven for decades using smallscale (. 50 physical qubit) demonstration systems, the main problem is achieving scalability using existing designs.

Individual atomic ions trapped by electromagnetic fields in a vacuum and manipulated using lasers have been a leading candidate for a physical substrate for QIP since the beginning, but scaling has been limited by the bulky free-space optics that are traditionally used for state manipulation and readout. CMOS chips with integrated photonics, on the other hand, can solve the scalability issue by tightly packing photodetectors for state readout, classical computing resources for timing and control, and optical waveguides and modulators for state manipulation onto the same chip. In recent years researchers have fabricated a planar ion trap in a CMOS foundry and addressed individual ions using photonic components built on a custom-fabricated ion trap, but the problem of CMOS-integrated state readout remains unaddressed. Current approaches to state readout use a large external lens and photomultiplier tube to detect state-dependent ion fluorescence.

Instead, fabricating silicon photodetectors directly below the trap location would eliminate large light collection optics and enable scaling of readout to greater numbers of ions by closing the sensing-to-manipulation loop on-chip. This thesis addresses this issue by developing hardware and methodology to perform detailed characterization of single-photon avalanche diodes (SPADs) integrated on a CMOS ion trap at cryogenic temperatures, showing that state readout with speed and fidelity comparable to the bulk optics approach is possible. Based on our results, state readout experiments using a CMOS ion trap with integrated SPADs are presently underway at the MIT Lincoln Laboratory.