Energy efficient sub-terahertz electrical interconnect

Abstract

With the end of Moore's Law and Dennard scaling in silicon platforms, coupled with the increase in computational demand across applications, the semiconductor industry has seen a move towards high-density compute leveraging multiple dies in package. These types of products have been partially enabled by short-reach, energy-efficient, high-speed interconnect in package. Big data and AI/ML applications have pushed the development of longer-reach, high-capacity, and energy efficient interconnect enabling connectivity between racks across large data centers. This work investigates and demonstrates a new interconnect technology that fills a meter-class interconnect gap in these applications. By leveraging the wide transmission bandwidth and low-losses associated with dielectric waveguides in the sub-THz regime (100 GHz - 1 THz), large baseband data rates are aggregated across multiple channels, multiplexed on to a single electrical channel, efficiently coupled into a dielectric waveguide, and transmitted between chips. In this work, enabling component technologies are developed and demonstrated, including planar broadband couplers and high-performance sub-THz multiplexers operating in the 220-330 GHz WR-3.4 band -- both technologies designed to ease implementation and packaging costs. Lastly, an end-to-end link is realized in a 130nm Silicon Germanium BiCMOS process and is demonstrated utilizing a small cross-section polymer dielectric waveguide. The link achieves 105 Gbps in a 250 ̄ 400 [mu]m² waveguide cross section, demonstrating a state of the art 330 Gbps/mm figure of merit and better than 5 pJ/bit energy efficiency.