Investigation of Ultra-Low Power CMOS GHz Circulator

Abstract

Quantum computing is a future solution for unprecedented computation power to solve today’s challenges, such as simulating molecules and forecasting natural disasters more accurately. A practical quantum computing system needs thousands or even millions of qubits. However, the quantum computing systems today have demonstrated operation with only a few to hundreds of qubits. CMOS circuits are candidates for readout and control circuits for a practical quantum computer for their compactness and scalability. Especially, building CMOS readout and control circuits at cryogenic temperatures can reduce power loss at the interface of the circuitry and the qubits and improve speed.

Circulators are one of the most common blocks in qubit readout circuits, but most cryogenic circulators today are bulky. This project investigated the design of scalable cryo-CMOS circulators. To reduce power consumption below the cooling budget in a cryogenic regime while maintaining losses and isolation performances, I took three approaches -1) decreasing the modulation frequency, 2) increasing the transistor size, and 3) using a more advanced technology node. Phase shifters and filters were redesigned to reduce the modulation frequency, and a full-duplexer was implemented based on the previous work [1], with TSMC 65 nm technology and Intel 22 nm technology. The circuit was simulated for both at room temperature and at 4 K.