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Unified Graph Framework: Optimizing Graph Applications across Novel Architectures

Author(s)
Hsu, Claire
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Advisor
Amarasinghe, Saman
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In Copyright - Educational Use Permitted Copyright MIT http://rightsstatements.org/page/InC-EDU/1.0/
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Abstract
High performance graph applications are crucial in a wide set of domains, but their performance depends heavily on input graph structure, algorithm, and target hardware. Programmers must develop a series of optimizations either on the compiler level, implementing different load balancing or edge traversal strategies, or on the architectural level, creating novel domain-specific accelerators optimized for graphs. In recent years, there has been rapid growth on the architectural end, with each novel architecture contributing new potential optimizations. To help compiler development scale with the growth of the architecture domain, we develop the Unified Graph Framework (UGF) to achieve portability for easy integration of novel backend architectures into a high-level hardware-independent compiler. UGF builds on the GraphIt domain-specific language, which divides algorithm specification from scheduling optimizations, and separates hardware-independent from hardwarespecific scheduling parameters and compiler passes. As part of UGF, we introduce GraphIR, a graph-specific, hardware-independent intermediate representation; an extensible scheduling language API that enables hardware-independent optimizations and programmer-defined hardware-specific optimizations; and the GraphVM, the compiler backend implemented for each hardware architecture. Lastly, we evaluate UGF by implementing a GraphVM for Swarm, a recently developed multicore architecture. We integrate several scheduling optimizations built around Swarm’s ability to speculate on fine-grained tasks in future loop iterations. When evaluated on five applications and 10 input graphs, UGF successfully generates highly optimized Swarm code and achieves up to 8x speedup over baseline implementations.
Date issued
2021-06
URI
https://hdl.handle.net/1721.1/139201
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology

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