Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems

Abstract

The Internet of Things (IoT) consists of an ever-growing network of wireless-connected electronic devices which are always collecting, processing and communicating data. While the IoT has inspired many new applications, these embedded devices have unique security challenges, thus making IoT security a major concern. Security architectures for IoT devices, both software and hardware, must be low-power and have low energy consumption, while still providing strong cryptographic guarantees and side-channel resilience. Network security protocols use a variety of cryptographic algorithms to achieve these goals. However, the associated computational complexity makes it extremely important to have low-power and energy-efficient embedded implementations of cryptography, especially public key algorithms.

The research presented in this thesis demonstrates the design, implementation and experimental validation of efficient next-generation cryptography for embedded systems using software optimization, hardware acceleration and software-hardware co-design, along with side-channel countermeasures. Using circuit, architecture and algorithm techniques, efficient hardware-accelerated implementations of elliptic curve cryptography, pairing-based cryptography, lattice-based cryptography and other post-quantum cryptography algorithms are demonstrated with up to two orders of magnitude energy savings compared to state-of-the-art software and hardware. These configurable hardware accelerators are further coupled with a low-power micro-processor to provide the flexibility to implement a wide variety of security protocols, thus enabling strong and affordable security for energy-limited IoT nodes.