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A high-performance retargetable simulator for parallel architectures

dc.contributor.advisorWilliam E. Weihl.en_US
dc.contributor.authorDellarocas, Chrysanthos, 1967-en_US
dc.date.accessioned2005-08-11T12:00:00Zen_US
dc.date.available2005-08-11T12:00:00Zen_US
dc.date.copyright1991en_US
dc.date.issued1991en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/13945
dc.descriptionThesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1991.en_US
dc.descriptionIncludes bibliographical references (leaves 94-97).en_US
dc.description.statementofresponsibilityby Chrysanthos Nicholas Dellarocas.en_US
dc.format.extent97 leavesen_US
dc.format.extent8056821 bytes
dc.format.extent8056581 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Scienceen_US
dc.titleA high-performance retargetable simulator for parallel architecturesen_US
dc.typeThesisen_US
dc.description.degreeM.S.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc24993035en_US


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