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dc.contributor.advisorStephen A. Ward.en_US
dc.contributor.authorMorrison, Joseph Dereken_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2005-08-10T17:32:01Z
dc.date.available2005-08-10T17:32:01Z
dc.date.copyright1989en_US
dc.date.issued1989en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/14200
dc.descriptionThesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989.en_US
dc.descriptionIncludes bibliographical references (leaves 101-102).en_US
dc.description.statementofresponsibilityby Joseph Derek Morrison.en_US
dc.format.extentviii, 102 leavesen_US
dc.format.extent8179615 bytes
dc.format.extent8179376 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleA scalable multiprocessor architecture using Cartesian Network-Relative Addressingen_US
dc.typeThesisen_US
dc.description.degreeM.S.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc22213147en_US


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