| dc.description.abstract | The lack of a high-performance and scalable superconducting memory has been a persistent issue in the field of superconducting computing for decades. There have been many attempts at addressing this issue; however, to-date no technology has been able to completely satisfy this demand. In this work we present a novel memory design based on superconducting nanowires controlled by localized thermal effects. Initial results from this design are very promising and suggest that with some further development, our design may satisfy the need for such a superconducting memory technology.
As superconducting nanowire electronics mature and become increasingly faster and more complex, the traditional reliance on off-chip microwave components has become unsustainable. In this thesis, we present the design and experimental results for a set of on-chip microwave devices, including bias tees, filters, detectors, couplers, and delay lines. In addition, by using the modeling developed for the memory, we make this set of microwave devices tunable through thermally controlling their kinetic inductance. To demonstrate the on-chip instrumentation that this library enables, a characterization of the thermal response of our tunable devices by means of an on-chip interferometer is presented. With the increasing complexity of our designs, we find ourselves in need of a new experimental apparatus to support our work. Finding no suitable solutions either commercially available or in literature, we developed a new versatile cryogenic experimental platform for nanowire electronics. The design presented here consolidates what was previously a number of discrete setups into one universal platform, while also greatly improving performance. Through the advances presented in this work, we have enabled the future realization of more complex nanowire-based superconducting electronics. | |
