Design of a Precision, Very Low 1/f Noise, Low Power, Rail-Rail I/O, Integrated Bi-CMOS Operational Amplifier
Name
Chavez-rhianc-meng-eecs-2022-thesis.pdf
Description
Thesis PDF
Size
1.9 MB
Format
Adobe PDF
Checksum (MD5)
3068009c6442aabff50544d422936bb7
Author(s)
Chavez, Rhian Austin
Advisor(s)
Bourque, Lance
Han, Ruonan
Date Issued
February 2022
Publisher
Massachusetts Institute of Technology
Abstract
The detailed design of a precision, very low 1/𝑓 noise, 100𝜇A, 30V, rail to rail input and output, integrated Bi-CMOS operational amplifier is presented. Necessity for such an amplifier in the current technological space is examined. Specific attention is given to the novel design of a stable current source requiring no more than approximately 50mV of overhead, for use with a very low noise native NMOS differential input pair. An improved technique for analyzing MOSFET 1/𝑓 noise in modern simulation environments is explored. Special consideration is given to the usage of native NMOS devices as the primary input pair, which are required in order to meet the low noise and zero input bias current requirements simultaneously. Detailed descriptions of key amplifier stages are given; rail to rail input, folded cascode, Monticelli rail to rail output, and Miller compensation. Finally, amplifier transient, spectral, and noise results are presented and discussed.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
In Copyright - Educational Use Permitted
Copyright MIT
Persistent DSpace Link
