Gate-geometry Dependence of Enhancement-mode p-GaN Gate High Electron Mobility Transistors

Abstract

While GaN-based transistors for power electronics have in many situations demonstrated technological superiority over conventional Si based devices, the development of GaN power electronics has only scratched the surface of the possibilities that lie ahead. The most promising device structure for power electronics is the enhancement-mode p-GaN Gate High Electron Mobility Transistor (HEMT) which matches the power, voltage, and efficiency of conventional GaN FETs but most importantly features a positive threshold voltage. This is achieved by the insertion of a Mg-doped GaN layer above the AlGaN/GaN heterostructure that is contacted by a Schottky metal. In this manner, the gate stack under positive gate bias features a back-to-back diode configuration with the reverse biased gate-metal/p-GaN Schottky diode in series with the forward biased p-GaN/AlGaN/GaN p-i-n barrier diode. An undesirable aspect of this configuration is a p-GaN intermediate node that is largely floating complicating device operation and understanding of device physics and reliability.

This thesis carries out a detailed study of the impact of gate geometry design, in particular the relative area of the p-i-n and the Schottky barrier junctions, on the operation and reliability of industrially prototyped p-GaN gate HEMTs. In particular, we study the impact of the length of an offset region at the edges of the gate stack that is not contacted by the Schottky metal. Our study reveals gate electrostatics that under steady-state conditions are set by gate current continuity across the two junctions. Further, a surprising preferential gate current is found to flow across the p-GaN/AlGaN/GaN diode in the offset region of the p-GaN layer. The combination of these two factors has a large influence on the steady-state figures of merit of the device.

We have also found that under pulsed gate conditions, for a short time, the gate electrostatics are dominated by a capacitive divider set by the p-i-n and Schottky barrier junctions in series. This gives rise to prominent transients that are dominated by the charging dynamics of the p-GaN node. The time constants also exhibit a prominent gate geometry dependence.

Finally, we have studied the positive bias temperature instability (PBTI) of the devices under prolonged gate voltage stress and its dependence on gate geometry. We discover both recoverable and permanent degradation phenomena and, in particular, a new permanent positive threshold shift that is uniquely associated with the gate offset region.

We postulate that incomplete magnesium activation in the p-GaN offset region might be responsible for the unique behavior of the gate offset region of p-GaN gate HEMTs.