GaN Complementary-Metal-Oxide-Semiconductor (CMOS) Technology

Abstract

In 2014, the Nobel prize in physics was jointly awarded to Prof. Isamu Akasaki, Prof. Hiroshi Amano, and Prof. Shuji Nakamura for the invention of the blue LED which enabled ubiquitous white lighting. The key innovative technology that underpinned the invention of blue-LED is the efficient doping of GaN with p-type dopants. For years p-GaN has been used only in optoelectronic devices such as LEDs and LASERs. In this thesis we demonstrate how p-GaN can be used to realize the next generation of efficient RF and power electronics. Apart from being a direct and wide band-gap semiconductor which can be useful for optoelectronic devices, GaN and its alloys have other material attributes like spontaneous and piezoelectric polarization, high electron mobility, and high saturation velocity for electrons. These properties enable n-channel GaN-based transistors to operate at a higher switching speed, and at a higher power density than their Si counterparts. To realize the full potential of GaN, the need for a complementary circuit technology cannot be overemphasized. A high performance GaN-Complementary-Metal-Oxide-Semiconductor (CMOS) technology could potentially find applications in data centers, electric vehicles, space electronics, on-chip power converters, beyond 5G base stations, and a plethora of other applications where Si falls short in terms of performance and efficiency. However, a major roadblock towards realizing such a technology is the lack of high-performance GaN p-channel transistors that can be monolithically integrated with GaN n-channel devices. This thesis develops key pathways to improve the current density of GaN p-channel transistors by demonstrating a self-aligned gate and a FinFET technology for the p-channel device. Our demonstrated GaN p-channel devices exhibit record performance in terms of on-current density, on-off ratio, subthreshold swing and on-resistance. This thesis for the first time demonstrates a GaN-CMOS technology on a 6-inch GaN-on-Si wafer by fabricating a monolithically integrated p-channel GaN transistor with an E-mode GaN n-channel device.