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Nexion: Enabling Concurrency on Architectures for Ordered Parallelism

Author(s)
Durfee, Robert Benjamin
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Advisor
Sanchez, Daniel
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In Copyright - Educational Use Permitted Copyright MIT http://rightsstatements.org/page/InC-EDU/1.0/
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Abstract
Achieving high performance on modern systems with many cores requires highly parallel applications. Conventional parallel systems require structuring applications into activities that are concurrent, i.e., that may interleave arbitrarily. Concurrency makes it easy for hardware to run these tasks in parallel. However, for most applications, concurrency is challenging to reason about and incurs costly synchronization overheads. To address this problem, recent work has proposed architectures that exploit ordered parallelism. These systems enforce a fixed, programmer-specified order among tasks, and execute tasks speculatively to extract parallelism. Ordered semantics enable parallelism without concurrency, avoiding its complexity, and it is a natural fit for many applications. However, concurrency is also a good fit for many applications, and establishing an order is unnatural and unnecessarily limits parallelism. We present Nexion, an execution model that supports concurrency alongside ordered parallelism. Programmers split applications into short tasks that can be given timestamps to specify order constraints. Groups of tasks can be marked as concurrent and will execute independently if no data is shared among them. If data is shared, Nexion ensures that tasks remain atomic and respect applicable timestamp orders. We extend Swarm, an architecture for ordered parallelism, with minimal additional state to implement Nexion. The implementation is distributed and only involves communication between tasks that share data. On evaluated benchmarks, Nexion improves overall scalability by up to 32× over software-only solutions and up to 2.4× over the Swarm baseline architecture.
Date issued
2022-05
URI
https://hdl.handle.net/1721.1/144784
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology

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