Geometrical Optimization of Planar Nano Vacuum Channel Transistors

Abstract

Nano vacuum devices have demonstrated tunneling emission in low voltages due to their 10 nm scale gaps that create order 10 GV/m electric fields with just 10 V. The small gaps give rise to ballistic transport through the channel, which combined with the low capacitances of the electrodes, gives rise to ultrafast response times. Nano vacuum channel devices have also exemplified robustness in the face of extreme radiation and temperature conditions [28, 18]. The design of nano vacuum devices is unintuitive due to the complicated and partially unknown physics governing their operation. In this thesis, we present an approach to performing shape optimization on nano vacuum channel devices based on an adaptation of a simulated-annealing [55] algorithm. We defined figures of merit to maximize the current in a diode, minimize the off-to-on current ratio in a transistor, and minimize the gate leakage current in a transistor. We implemented a finite element electrostatic simulation to calculate the emission-current-density profiles on emitting tips in diodes and transistors. We also implemented a heuristic to particle tracking to speed up the simulations and optimization of transistors.

Using the optimization framework developed in this work, we are able to reach device designs that achieve a 6-orders-of-magnitude performance improvement compared to the initial geometry in approximately 10,000 optimization steps. For each emission model assumed, we uncover unique geometrical features that enhance the performance of devices on figure of merit of interest.

This work establishes a free and open-source framework for electronic device optimization. Using this framework, device designers and engineers can spend less time, money, and research efforts on developing efficient and high performing devices.